Analog Layout Engineer| Shanghai | 2+ years experience

PI Semi is founded by a team of industry veterans with a successful track record designing and marketing quality analog and mixed signal ICs, a market enjoying $60B in its annual turnover worldwide. Our core IPs and products support such applications as highspeed optical communications, RF bias for 5G infrastructure, medical devices and systems, BMS, industrial control, and automotive ADAS systems and so on. To serve these markets, we are building a portfolio of precision analog IPs that enable high resolution ADCs, precision DACs, voltage references, high voltage drivers and many other products. Those products can be standard products, but can also be custom made solutions per customer requirements. The company is headquartered in Shenzhen, with design centers being staffed in Shanghai and Bangalore, India.

We are looking for Layout Engineers to join our team working on leading edge precision analog products in CMOS and BCD processes.

We welcome engineers who share our values and who are committed to grow with us. The successful candidates will enjoy equity ownership, besides competitive salaries and benefits.

Responsibilities

● Responsible for block level layoutsShould be able to help with top level layout floor planning.

● Proven capability at block level floor planning, power routing, area and schedule estimations.

● Understanding of multiple voltage domains and related layout techniques.

● Communicate with design engineers to negotiate any necessary layout trade-offs as needed to build complex analog block level layout in CMOS and BCD technologies.

● Meet stringent matching, performance, area and power requirements while conforming to all PDV design requirements.

● Collaboration with digital P&R, IO & ESD design.

● Recognize failure prone circuit and layout structures.

● Debug and drive resolutions to Physical Design Kit issues, DRC/LVS/ERC improvements with respect to layouts.

Qualifications

● 2+ years experience creating custom analog/mixed-signal layouts at chip, block, and device levels in CMOS and BCD technologies.

● Expertise with Cadence Virtuoso XL schematic driven layout design flow, Virtuoso Floor Planning, Constraint Driven Layout, and extraction flows.

● Expertise using Mentor Graphics Calibre design verification suite (DRC, LVS, ERC); high proficiency with interpretation, debug, and understanding of results.

● Strong experience with high performance analog layout techniques for device matching, common centroid layout, isolation, shielding, use of dummy devices, parasitic sensitivities, high speed routing, and also chip level electromigration, IR drop, self-heating, cross coupling capacitance and DFM practices.

● Good understanding of package needs and constraints with respect to chip level.

● Scripting experience in PERL or SKILL is considered a plus.

● English Level: Work proficiency.

Apply:

careers@pisemi.cn